In any broadcast video system it is important that the video being displayed by the television receiver (decoder) is accepted and processed at the same rate as that of the broadcast side (encoder). This rate synchronization is attained by use of encoder-side timestamps that are transmitted in a transport stream as a special clock-reference packet. For example, the PCR (Program Clock Reference) packet in MPEG contains a 42-bit counter based on a 27 MHz reference clock in the encoder. In MPEG transmissions, PCR packets arrive no more than 100 milliseconds apart.
On the decoder side, the arrival of each PCR packet is recorded with the System Time Clock (STC). The System Time Clock is based on a 27 MHz reference clock local to the receiver. A basic synchronization system consists typically of a first order feedback loop. Each incoming PCR value is subtracted from the corresponding decoder's STC value, and the filtered difference (times a proportionality constant) is the control voltage for the voltage controlled crystal oscillator (VCXO) that supplies the reference clock to the decoder/display chip. This feedback loop stabilizes with the correct frequency, ensuring a lock between the encoder and the decoder reference clocks.
As these video receiver systems are becoming more-and-more sophisticated, the requirement to handle multiple high-definition channels simultaneously is getting more prominent. Such a situation could arise either in systems with multiple tuners or in systems required to process multiple channels within the same transport stream from a single tuner. The additional channels may be used for Picture-In-Picture (PIP) display, viewing one channel while recording other channels, or driving multiple independent displays.
In a system that simultaneously handles two channels, for example, with independent rates, locking the audio/video rendering clock for both channels to one input channel can result in the need to drop frames or replicate frames due to the varying input rates of the two channels. Additionally, if there are time-base errors in the input channel used for locking, both channel outputs will be impacted.